AN 531: Reducing Power with Hardware Accelerators

Introduction Reducing power consumption in embedded products that use FPGAs is increasingly important, particularly for battery-powered applications or to reduce heat or cost. You can use parallel algorithms to exploit the parallel architecture of FPGA devices to accomplish more work per clock cycle, allowing you to lower the clock frequency. High-level development tools such as SOPC Builder and the Nios® II C-to-Hardware Acceleration Compiler (C2H) can help you use the power-saving potential of the FPGA hardware by easily adding hardware accelerators and lowering clock frequencies.